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Ordering number : EN5945
CMOS IC
LC72321N, 72322N, 72323N
Single-Chip Microcontrollers with Built-in LCD Driver and PLL Circuits
Overview
The LC72321N, LC72322N, and LC72323N are singlechip microcontrollers designed for electronic tuning in radio receivers and include an on-chip LCD driver circuit and a PLL circuit that operates at 150 MHz. These microcontrollers feature a large program ROM capacity, an efficient instruction set, and powerful hardware. Note that the LC72321N, LC72322N, and LC72323N provide functions equivalent to the LC72321, LC72322, and LC72323, and are software compatible with those products.
Functions
* * * * Serial I/O (LC72321N only) Timers: 80 s, 1 ms, 2 ms, and 5 ms periods Stack levels: 8 levels Beep tone outputs: Six frequencies (2.08, 2.25, 2.5, 3.0, 3.75, and 4.17 kHz) (LC72321N only) High-speed programmable divider General-Purpose counters HCTR: Frequency measurement LCTR: Frequency or period measurement LCD drive circuit: Drives 56 segments with 1/2-duty 1/2-bias drive Program memory (ROM): 16 bits x 4095 words (8K bytes) LC72321N and LC72322N 16 bits x 3071 words (6K bytes) LC72323N Data memory (RAM): 4 bits x 256 words All instructions are single-word instructions.
Cycle times: 2.67 s, 13.33 s, or 40.00 s (option) Unlock flip-flop: 0.55 s and 1.1 s detection Timer flip-flop: 1 ms, 5 ms, 25, ms, and 125 ms Input ports*: One dedicated key input port, and one high-voltage port * Output ports*: Two dedicated key output ports, one high-voltage opendrain port Two CMOS output ports (one of which can be switched over to function as an LCD driver output) Seven CMOS output ports (Switching these ports over to function as LCD driver outputs is supported as an option.) * I/O ports*: One port switchable between input and output in 4-bit units One port switchable between input and output in 1-bit units
*: Each port consists of 4 bits.
* * * *
Continued to next page.
Package Dimensions
unit: mm 3174-QFP80E
[LC72321N, 72322N, 72323N]
23.2 20.0 1.0
0.8 64 65 40 0.8 0.35 41
* *
* *
1.6 0.15
17.2 14.0
0.8
2.7
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
21.6
0.8
SANYO: QFP80E (QIP80E)
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N1698RM(OT) No. 5945-1/13
0.8
1
24
3.0max
* *
1.6
80
25
15.6
LC72321N, 72322N, 72323N
Continued from preceding page.
* Function that detects uncontrolled looping and jumps to a specified address * Voltage detection reset circuit * One 6-bit A/D converter * Two 8-bit A/D converters (PWM) (LC72321N and LC72322N only) * One external interrupt (The external interrupt can be selected to be one of the following: an external interrupt, Pin Assignment
N-channel open-drain output-only pins with 15-V voltage handling capacity PH2 and PH3 can be switched to be used with the D/A converter.*2 PH1 can be switched to be used as the beep tone function pin.*1 Input-only pins The input voltage handling capacity is 13 V (maximum rating)
* * * * *
an internal timer interrupt, or the serial I/O circuit (in the LC72321N).) RAM data retention in hold mode Sensing flip-flop for hot/cold start discrimination PLL: 4.5 to 5.5 V CPU: 3.5 to 5.5 V RAM: 1.3 to 5.5 V
High voltage handling capacity input ports (maximum ratings) INT, RES, ADI SNS, HOLD 13 V
CMOS I/O These pins can be switched between input and output in 1-bit units.
S1 through S28 can be switched to function as general-purpose CMOS output ports. (In the option specifications)
CMOS I/O These pins can be switched between input and output in 4-bit units. PE1, PE2, and PE3 can be switched to be used by the SI/O circuit.*1
CMOS output-only pins CMOS output-only pins (for key outputs or similar functions) These are unbalanced CMOS outputs and pairs of these pins may be shorted together.
Input-only pins (for key inputs or similar functions) The presence or absence of built-in pulldown resistors can be selected.
Can be switch to function as LCD segment outputs. CMOS output-only pins
Option Notes:*1. Only possible with the LC72321N *2. Only possible with the LC72321N and LC72322N
No. 5945-2/13
LC72321N, 72322N, 72323N Block Diagram
Notes:*1. Only possible with the LC72321N *2. Only possible with the LC72321N and LC72322N
No. 5945-3/13
LC72321N, 72322N, 72323N
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Symbol VDD max VIN1 VIN2 Output voltage VOUT1 VOUT2 IOUT1 Output current IOUT2 IOUT3 IOUT4 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg HOLD, INT, RES, ADI, SNS Port G Inputs other than VIN1 Port H Outputs other than VOUT1 All the port D and H pins All the port E and F pins All the port B and C pins S1 to S28 and port I Ta = -40 to +85C Conditions Rating -0.3 to +6.5 -0.3 to +13 -0.3 to VDD + 0.3 -0.3 to +15 -0.3 to VDD + 0.3 0 to 5 0 to 3 0 to 1 0 to 1 300 -40 to +85 -45 to +125 Unit V V V V V mA mA mA mA mW C C
Input voltage
Allowable Operating Ranges at Ta = -40 to +85C, VDD = 3.5 to 5.5 V
Parameter Symbol VDD1 Supply voltage VDD2 VDD3 VIH1 VIH2 High-level input voltage VIH3 VIH4 VIH5 VIH6 VIL1 VIL2 VIL3 Low-level input voltage VIL4 VIL5 VIL6 VIL7 fIN1 fIN2 fIN3 Input frequency fIN4 fIN5 fIN6 fIN7 fIN8 VIN1 VIN2 Input amplitude VIN3 VIN4, 5 VIN6, 7 Input voltage range VIN8 Conditions CPU and PLL operating CPU operating Memory retention Port G RES, INT, HOLD SNS Port A Ports E and F LCTR (period measurement), VDD1, PE1, and PE3 Port G RES, INT, PE1, PE3 SNS Port A PE0, PE2, and port F LCTR (period measurement) and VDD1 HOLD XIN FMIN, VIN2, VDD1 FMIN, VIN3, VDD1 AMIN (L), VIN4, VDD1 AMIN (H), VIN5, VDD1 HCTR, VIN6, VDD1 LCTR (frequency), VIN7, and VDD1 LCTR (period), VIH6, VIL6, and VDD1 XIN FMIN FMIN AMIN LCTR, HCTR ADI Ratings min 4.5 3.5 1.3 0.7 VDD 0.8 VDD 2.5 0.6 VDD 0.7 VDD 0.8 VDD 0 0 0 0 0 0 0 4.0 10 10 0.5 2.0 0.4 100 1 0.50 0.10 0.15 0.10 0.10 0 4.5 typ max 5.5 5.5 5.5 8.0 8.0 8.0 VDD VDD VDD 0.3 VDD 0.2 VDD 1.3 0.2 VDD 0.3 VDD 0.2 VDD 0.4 VDD 5.0 130 150 10 40 12 500 20x103 1.5 1.5 1.5 1.5 1.5 VDD Unit V V V V V V V V V V V V V V V V MHz MHz MHz MHz MHz MHz kHz Hz Vrms Vrms Vrms Vrms Vrms V
No. 5945-4/13
LC72321N, 72322N, 72323N Electrical Characteristics in the Allowable Operating Ranges
Parameter Hysteresis Rejected pulse width Power down detection voltage Symbol VH PREJ VDET IIH1 IIH2 High-level input current IIH3 IIH4 IIH5 IIL1 Low-level input current IIL2 IIL3 IIL4 Input floating voltage Pull-down resistance High-level output off leakage current Low-level output off leakage current VIF RPD IOFFH1 IOFFH2 IOFFH3 IOFFL1 IOFFL2 VOH1 VOH2 VOH3 High-level output voltage VOH4 VOH5 VOH6 VOH7 VOL1 VOL2 VOL3 VOL4 Low-level output voltage VOL5 VOL6 VOL7 VOL8 Output middle level voltage A/D converter error VM1 IDD1 IDD2 IDD3 Current drain IDD4 INT, HOLD, RES, ADI, SNS, port G: VI = 5.5 V Ports A, E, and F: with ports E and F set to output off, with the port A RPD disabled, VI = VDD XIN: VI = VDD = 5.0 V FMIN, AMIN, HCTR, LCTR: VI = VDD = 5.0 V Port A: RPD enabled, VI = VDD = 5.0 V INT, HOLD, RES, ADI, SNS, port G: VI = VSS Ports A, E, and F: with ports E and F set to output off, with the port A RPD disabled, VI = VSS XIN: VIN = VSS FMIN, AMIN, HCTR, LCTR: VI = VSS Port A: RPD enabled Port A: RPD enabled, VDD = 5.0 V EO1, EO2: VO = VDD Ports B, C, D, E, F, and I: VO = VDD Port H: VO = 13 V EO1, EO2: VO = VSS Ports B, C, D, E, F, and I: VO = VSS Ports B and C: IO = 1 mA Ports E and F: IO = 1 mA EO1, EO2: IO = 500 A XOUT: IO = 200 A S1 to S28 and port I: IO = -0.1 mA Port D: IO = 5 mA COM1, COM2: IO = 25 A Ports B and C: IO = 50 A Ports E and F: IO = 1 mA EO1, EO2: IO = 500 A XOUT: IO = 200 A S1 to S28 and port I: IO = 0.1 mA Port D: IO = 5 mA COM1, COM2: IO = 25 A Port H: IO = 5 mA COM1, COM2: VDD = 5.0 V, IO = 20 A ADI: VDD1 VDD1, fIN2 = 130 MHz VDD2, PLL circuit stopped, CT = 2.67 s (hold mode, see figure 1) VDD2, PLL circuit stopped, CT = 13.33 s (hold mode, see figure 1) VDD2, PLL circuit stopped, CT = 40.00 s (hold mode, see figure 1) VDD = 5.5 V, oscillator circuit stopped, Ta = 25C (backup mode, see figure 2) IDD5 VDD = 2.5 V, oscillator circuit stopped, Ta = 25C (backup mode, see figure 2) 1 A 0.3 (150 ) 0.75 2.0 -1/2 15 1.5 2.5 0.5 VDD - 1.0 VDD - 1.0 VDD - 1.0 VDD - 1.0 VDD - 1.0 VDD - 0.75 VDD - 0.5 VDD - 0.3 0.5 1.0 2.0 1.0 1.0 1.0 1.0 1.0 0.75 (400 ) 2.0 3.0 +1/2 20 0.01 75 100 0.01 2.0 4.0 5.0 10 2.0 4.0 5.0 10 50 3.0 3.0 15 30 0.05 VDD 200 10 3.0 5.0 10 3.0 VDD - 2.0 VDD - 1.0 VDD - 0.5 Conditions LCTR(period), RES, INT, PE1, PE3 SNS 2.7 3.0 0.1 VDD Ratings min typ max V 50 3.3 3.0 3.0 15 30 s V A A A A A A A A A V k nA A A nA A V V V V V V V V V V V V V V V V LSB mA mA Unit
1.0
mA
0.7
mA
5
A
No. 5945-5/13
LC72321N, 72322N, 72323N Test Circuit Diagrams
Note: PB to PF, PH, and PI must all be left open. However, PE and PF should be selected for output.
Figure 1 IDD2 to IDD4 in Hold Mode
Note: PA to PI, S1 to S24, COM1, and COM2 must all be left open.
Figure 2 IDD5 in Backup Mode
No. 5945-6/13
LC72321N, 72322N, 72323N Pin Function
Pin No. Pin Description Low-threshold input-only port. 35 34 33 32 PA0 PA1 PA2 PA3 Can be used for functions such as key data acquisition. Pull-down resistors can be specified as an option. This option is specified in a 4-pin unit, and cannot be specified in single pin units. Input is disabled in backup mode. Input I/O
I/O circuit
30 29 28 27 26 25 24 23
PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 Output-only ports. Since the output transistor circuits are unbalanced CMOS outputs, these outputs can be effectively used for functions such as key scan timing. These ports go to the high-impedance state in backup mode. These ports output a low level after a reset (when RES is set low). Output
Output-only port. 22 21 20 19 PD0 PD1 PD2 PD3 These are normal CMOS outputs. This port goes to the high-impedance state in backup mode. This port outputs a low level after a reset (when RES is set low). I/O port. The input/output state is selected as follows: Once an input instruction (IN, TPT, or TPF) is executed, the port switches to the input state and remains in that state. PE0 PE1/SCK Once an output instruction (OUT, SPB, RPB) is executed, the port switches to the output state and remains in that PE2/SO state. Note that PE1, PE2, and PE3 are also used as the PE3/SI serial I/O port. These pins go to the input state after a reset. This port goes to the input state with input disabled in backup mode. I/O port. 14 13 12 11 PF0 PF1 PF2 PF3 The FPC instruction is used for switching the port function between input and output. Input or output can be specified in single pin units. This port is set to its input function after a reset. This port goes to the input state with input disabled in backup mode. I/O
18 17 16 15
6 5 4 3
PG0 PG1 PG2 PG3 Input-only port. Input is disabled in backup mode. Input
Continued on next page.
No. 5945-7/13
LC72321N, 72322N, 72323N
Continued from preceding page.
Pin No.
Pin Output-only port.
Description
I/O
I/O circuit
10 9 8 7
PH0 PH1/BEEP*1 PH2/DAC1*2 PH3/DAC2*2
Since these ports are high-voltage handling n-channel transistor open-drain outputs, they are effective for use in band power supply switching. Note that PH1, PH2, and PH3 have shared functions as the BEEP*1, DAC1, and DAC2 outputs, respectively.*2 This port goes to the high-impedance state in backup mode and after a reset (when the RES pin is set low). Output-only port. These pins are CMOS outputs, but can be switched to function as LCD driver outputs. The SS and RS instructions are used to switch the port function. The port function cannot be switched in single pin units. The LCD driver function is selected and a display off signal is output when RES is low and when power is first applied. In backup mode the output is held at the low level. Note that when use as a general-purpose port is specified as an option, the contents of IPORT are output when LPC is 1, and the contents of the generalpurpose output port latch is are output when LPC is 0.
Output
39 38 37 36
PI0/S25 PI1/S26 PI2/S27 PI3/S28
Output
LCD driver segment outputs. The fame frequency is 100 Hz. The drive type is 1/2-duty 1/2-bias drive. 63 to 40 S1 to S24 A display off signal is output when RES is low and when power is first applied. In backup mode the outputs are held at the low level. An option is available that allows these pins to be used as general-purpose outputs. Output
LCD driver common outputs. The drive type is 1/2-duty 1/2-bias drive. 65 64 COM1 COM2 These pins output the same signal as is output during normal operation when RES is low and when power is first applied. In backup mode these outputs are held at the low level. Output
FM VCO (local oscillator) input. 74 FM IN Input must be supplied through a coupling capacitor. The input frequency range is 10 to 130 MHz. AM VCO (local oscillator) input. Input must be supplied through a coupling capacitor. 75 AM IN The pin frequency band can be selected with the PLL instruction CW1 bit. High (2 to 40 MHz) SW Low (0.5 to 10 MHz) LW and MW Notes:*1. Only supported by the LC72321N *2. Only supported by the LC72321N and LC72322N Input
Continued on next page.
No. 5945-8/13
LC72321N, 72322N, 72323N
Continued from preceding page.
Pin No.
Pin Universal counter input.
Description Input must be supplied through a coupling capacitor.
I/O
I/O circuit
70
HCTR
The input frequency range is 0.4 to 12 MHz This pin can be used effectively for FM IF or AM IF counting. Universal counter input. Input must be supplied through a coupling capacitor when the input frequency is in the range 100 to 500 kHz. Input
71
LCTR
No input coupling capacitor is required when the input frequency is in the range 1 Hz to 20 kHz. This pin can be used effectively for AM IF counting. This pin can also be used as a normal input port.
A/D converter input. 69 ADI This converter requires 1.28 ms to perform a 6-bit sequential comparison conversion. Full scale (a data value of 3F (hexadecimal)) corresponds to (63/96) time VDD. Input
External interrupt request input. 66 INT An interrupt occurs when the INTEN flag is set with the SS instruction and a falling edge is input. This pin can also be used as a normal input port. Input
77 78
EO1 EO2
These pins are used as the reference frequency output and the phase comparator error output for the programmable divider. A charge pump circuit is built in. EO1 and EO2 are the same.
Output
72
SNS
Input used to recognize power failures when the IC is in backup mode. This pin can also be used as a normal input port. Input used to set the IC to hold mode. The IC switches to hold mode when the HOLDEN flag is set with the SS instruction and the HOLD pin is set low. A high-voltage handling circuit is used so that this pin can be linked to the power switch in typical systems. System reset input.
Input
67
HOLD
Input
68
RES
Applications must hold this input low for at least 75 ms to effect a power on reset. To start a reset, this pin must be held low for a full 6 base clock cycles.
Input
1 80
XIN XOUT
Crystal oscillator connections (4.5 MHz) Feedback resistors are built in.
Input Output
2 79 31, 73 76
TEST1 TEST2 VDD VSS
IC test pins. These pins must be either left open or connected to VSS. Power supply
--
--
--
--
No. 5945-9/13
LC72321N, 72322N, 72323N Mask Options
Option WDT (watchdog timer) selection Selections WDT present WDT absent Pull-down resistors enabled Pull-down resistors disabled 2.67 s Cycle time selection (3 options) 13.33 s 40.00 s Switching of the LCD segment driver pins to function as general-purpose output ports LCD ports General-purpose output ports
Port A (key input port) pull-down resistor selection
Development Environment * The LC72P321 is used as the OTP version. * The LC72EV321 is used as the evaluation chip. * A total debugging system is available in which an evaluation board (TB-72EV32) and a multi-function emulator (RE32) are controlled by a personal computer.
No. 5945-10/13
LC72321N, 72322N, 72323N LC72321N, LC72322N, and LC72323N Instruction Set Abbreviations: ADDR b B C DH DL I M N Pn r () ( )N
Instruction group Mnemonic AD ADS Addition instructions AC ACS AI AIS AIC AICS SU SUS 1st r r r r M M M M r r
: Program memory address [12 bits] : Borrow : Bank number [2 bits] : Carry : Data memory address high (Row address) [2 bits] : Data memory address low (Column address) [4 bits] : Immediate data [4 bits] : Data memory address : Bit position [4 bits] : Port number [4 bits] : General register (One of the locations 00 to 0FH in bank 0) : Contents of register or memory : Contents of bit N of register or memory
2nd M M M M I I I I M M Function Add M to r Add M to r, then skip if carry Add M to r with carry Add M to r with carry then skip if carry Add I to M Add I to M, then skip if carry Add I to M with carry Add I to M with carry, then skip if carry Subtract M from r Subtract M from r, then skip if borrow Subtract M from r with borrow Subtract M from r with borrow, then skip if borrow Subtract I from M Subtract I from M, then skip if borrow Subtract I from M with borrow Subtract I from M with borrow, then skip if borrow Skip if r equals M Operation r (r) + (M) r (r) + (M) skip if carry r (r) + (M) + C r (r) + (M) + C skip if carry M (M) + I M (M) + I skip if carry M (M) + I + C M (M) + I + C skip if carry r (r) - (M) r (r) - (M) skip if carry r (r) - (M) - b r (r) - (M) - b skip if borrow M (M) - I M (M) - I skip if borrow M (M) - I - b Machine code D15 14 13 12 0100 0100 0100 0100 0101 0101 0101 0101 0110 0110 11 10 9 8 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 DH DH DH DH DH DH DH DH DH DH 7654 DL DL DL DL DL DL DL DL DL DL 3 2 1 D0 Rn Rn Rn Rn I I I I Rn Rn
Operands
SB Subtraction instructions
r
M
0110
1
0
DH
DL
Rn
SBS
r
M
0110
0
0
DH
DL
Rn
SI SIS
M M
I I
0111 0111
0 0
0 1
DH DH
DL DL
I I
SIB
M
I
0111
1
0
DH
DL
I
SIBS
M
I
M (M) - I - b skip if borrow rM skip if zero rM skip if not borrow (r) (M) M-I skip if zero M-I skip if not borrow (M) I
0101
1
1
DH
DL
I
SEQ Comparison instructions
r
M
0000
0
1
DH
DL
Rn
SGE
r
M
Skip if r is greater than or equal to M
0000
1
1
DH
DL
Rn
SEQI
M
I
Skip if M equal to I
0011
0
1
DH
DL
I
SGEI
M
I
Skip if M is greater then or equal to I
0011
1
1
DH
DL
I
Continued on next page.
No. 5945-11/13
LC72321N, 72322N, 72323N
Continued from preceding page.
Instruction group Logical operation instructions Mnemonic AND OR EXL LD ST Operands 1st M M r r M 2nd I I M M r Function AND I with M ORI with M Exclusive OR M with r Load M to r Store r to M Move M to destination M referring to r in the same row Move source M referring to r to M in the same row Move M to M in the same row Move I to M Load M to PLL registers Test M bits, then skip if all bits specified are true Test M bits, then skip if all bits specified are false Jump to the address Call subroutine Return from subroutine Operation M (M) I M (M) I r (r) (M) r (M) M (r) (DH, Rn) (M) Machine code D15 14 13 12 0011 0011 0010 1000 1000 11 10 9 8 0 1 0 0 0 0 0 0 0 1 DH DH DH DH DH 7654 DL DL DL DL DL 3 2 1 D0 I I Rn Rn Rn
Transfer instructions
MVRD
r
M
1000
1
0
DH
DL
Rn
MVRS
M
r
M (DH, Rn)
1000
1
1
DH
DL
Rn
MVSR MV1 PLL
M1 M M
M2 I r
(DH, DL1) (DH, DL2) MI PLL r PLL DATA
1001 1001 1001
0 0 1
0 1 0
DH DH DH
DL1 DL DL
DL2 I Rn
Bit test instructions
TMT
M
N
if M (N) = all 1, then skip
1010
0
1
DH
DL
N
TMF
M
N
if M (N) = all 0, then skip PC ADDR Stack (PC) + 1 PC Stack PC Stack BANK Stack CARRY Stack if timer F/F = 0, then skip
1010
1
1
DH
DL
N
Jump and subroutine instructions
JMP CAL RT
ADDR ADDR
1011 1100 1101 0100
ADDR (12 bits) ADDR (12 bits) 0000 0000
RTI
Return from interrupt
1101
0101
0000
0000
Flip-flop test instructions
TTM
N
Test timer F/F then skip if it has not been set Test unlock F/F then skip if it has not been set Set status register
1101
0110
0000
N
TUL
N
if UL F/F = 0, then skip (Status register 1) N1 (Status register 1) N0 if (Status register 2) N = all 1, then skip if (Status register 2) N = all 0, then skip BANK B
1101
0111
0000
N
Status register instructions
SS
N
1101
1100
0000
N
RS
N
Reset status register Test status register true Test status register false
1101
1101
0000
N
TST
N
1101
1110
0000
N
TSF
N
1101
1111
0000
N
Bank switching instructions
BANK
B
Select Bank
1101
00
B
0000
0000
Continued on next page.
No. 5945-12/13
LC72321N, 72322N, 72323N
Continued from preceding page.
Instruction group Mnemonic Operands 1st M 2nd I Function Output segment pattern to LCD digit direct Output segment pattern to LCD digit through PLA Input port data to M Output contents of M to port Set port bits Reset port bits Test port bits, then skip if all bits specified are true Test port bits, then skip if all bits specified are false Set I to UCCW1 Operation LCD (DIGIT) M Machine code D15 14 13 12 1110 11 10 9 8 00 DH 7654 DL 3 2 1 D0 DIGIT
LCD
LCP
M
I
LCD (DIGIT) PLA M M (Port (P)) (Port (P)) M (Port (P)) N 1 (Port (P)) N 0 if (Port (P)) N = all 1, then skip if (Port (P)) N = all 0, then skip UCCW1 I UCCW2 I FPC Latch N Stop clock if HOLD = 0 DAreg DAC DATA SIOCW I1, I2 M SIOreg SIOreg M BEEPreg I
1110
01
DH
DL
DIGIT
IN I/O instructions OUT SPB RPB
M M P P
P P N N
1110 1110 1111 1111
10 11
DH DH
DL DL P P
P P N N
0000 0101
TPT
P
N
1111
1010
P
N
TPF
P
N
1111
1111
P
N
Universal counter instructions
UCS
I
0000
0001
0000
I
UCC FPC CKSTP
I N
Set I to UCCW2 F port I/O control Clock stop
0000 0001 0001 0000 0001 0001 0001 0001 0000
0011 0000 0001 0010 0011 10 01 DH DH
0000 0000 0000 0000 I1 DL DL 0000 0000
I N 0000 I I2 I I I 0000
Other instructions
DAC SIO SIOL SIOS BEEP NOP
I I1 M M I I2 I I
Load M to D/A registers Serial I/O control Load SIOreg to M Store M to SIOreg Beep control No operation
0010 0000
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any and all SANYO products described or contained herein fall under strategic products (including services) controlled under the Foreign Exchange and Foreign Trade Control Law of Japan, such products must not be exported without obtaining export license from the Ministry of International Trade and Industry in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of November, 1998. Specifications and information herein are subject to change without notice. PS No. 5561-13/13

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